A large number of I/O pins of a computer chip are used to provide signals for the chip's maintenance and infrastructure and are not used for functional use or for traffic flow. Most of these signals either specify a static setting or are used in functions which are only needed in the initialization of the chip. During functional operation mode of the chip, all these signals are supposed to remain at a static value. However, sometimes, the development of shorts and opens or other fail mechanisms such as the injection of noise by induction will cause the signal integrity to be compromised despite all prior verification and signal noise analysis.
Current chip implementations do not provide a mechanism to check the integrity of these signals, so that a failure or a voltage level change of any of these signals at a point in time during functional operation leads to unexpected and highly undesired effects. Due to the nature of these control signals, it is usually difficult or impossible to track the pattern of the resulting errors down to the causing failing signal, which might, for example, control a phase locked loop (PLL) or a part of a clock tree.